The present invention relates generally to level shifters or translator circuits and more specifically to a level translator circuit which converts a single polarity signal into a dual polarity peak-to-peak signal.
A typical example of prior art interface or buffer circuits are U.S. Pat. Nos. 4,677,321 to Bacrania and 4,380,710 to Cohen et al., both assigned to Harris Corporation. These circuits are for converting single polarity TTL input signals to single polarity larger value CMOS level signals. Both circuits generally include differential inputs with a current mirror driving the output inverters. Techniques are included to increase the speed of operation as well as to compensate for manufacturing variances.
Another interface or level shifted circuit with speed-up operation is described in U.S. Pat. No. 4,450,371 to Bismarck. In this circuit, large capacity or low resistance field effect transistors P1A and P2A are provided and responsive to output level transitions to pull the respective node high to VDD. Once the transition is substantially effected, P1A or P2A are turned off leaving the smaller devices P1 or P2 on. The size of the devices P1A and P2A is necessary because they must overcome the currents of N1 and N2 previously tied to the node. Because of the use of the output logic, there is a substantial delay in the pull up of the node as illustrated by the drawings in FIG. 3. The number of devices in the output circuit necessarily increases the area required for the device, as well as adding delay of operation.
Thus, it is an object of the present invention to provide a level translator circuit which takes a single polarity signal and converts it into a bipolarity signal.
Another object of the present invention is to provide a faster level translator.
A still further object of the present invention is to provide a fast level translator with low power dissipation.
An even further object of the present invention is to provide a fast level translator with a minimum number of devices and thus reduce area.
A still even further object of the present invention is to provide a fast level translator without the use of passive components such as resistors.
A still even further object of the present invention is to provide a fast level translator which allows adjustment of the rise and fall times by adjusting the minimum number of device characteristics.
An even further object of the present invention is to provide a fast level translator which draws power only during switching transitions.
These and other objects of the invention are attained by providing a translating circuit between an input inverting circuit and an output circuit having a first and second field effect transistor with their source-drain paths connected between a first voltage terminal and first and second node, respectively, and their gates cross-coupled to the second and first nodes, respectively. Third and fourth field effect transistors have their source-drain paths connected between a second voltage terminal and the respective first and second nodes and their gates connected to the output and input, respectively, of the input inverter. Fifth and sixth field effect transistors have their source-drain paths connected between a third voltage terminal and a respective first and second nodes, and their gates connected one to the input and one to the output of the input inverter such that the third and sixth transistors are on together and the fourth and fifth transistors are on together. The output circuitry is connected to the second node. The fifth and sixth transistors pull their respective first and second nodes to the voltage at the third voltage terminal quicker than the contribution produced by the first and second transistors, respectively.